器件名称: 74AC378LCQR
功能描述: Parallel D Register with Enable
文件大小: 175.98KB 共8页
简 介:54AC 74AC378 Parallel D Register with Enable
March 1993
54AC 74AC378 Parallel D Register with Enable
General Description
The ’AC378 is a 6-bit register with a buffered common Enable This device is similar to the ’AC174 but with common Enable rather than common Master Reset
Features
Y Y Y Y Y
6-bit high-speed parallel register Positive edge-triggered D-type inputs Fully buffered common clock and enable inputs Input clamp diodes limit high-speed termination effects Standard Military Drawing (SMD) ’AC378 5962-91605
Logic Symbols
Connection Diagrams
Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC
TL F 10231–1 TL F 10231 – 3
IEEE IEC
TL F 10231 – 2
TL F 10231–4
Pin Names E D0 – D5 CP Q0 – Q5
Description Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Edge) Outputs
FACTTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 10231 RRD-B30M75 Printed in U S A
Functional Description
The ’AC378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q inputs The Clock (CP) and Enable (E) inputs are common to all flip-flops When the E input is LOW new data is entered into the register on the LOW-to-HIGH transition of the CP input When the E input is HIGH the register will retain the present data independent of the CP input
Truth Table
Inputs E H L L CP L L L Dn X H L Output Qn No Change H L
H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH ……