基于TMS320C6713和FPGA的数字电源控制模块设计

DSP控制程序图和数字PWM流程图如图2和图3所示。

下面给出的是用VHDL实现的死区发生器：

entiey dead_generator is

port(

clk,pa :in std_logic;

ah,al :out std_logic;

dead_time:in std_logic_vector(11 downto 0);

count :inout std_logic_vector(11 downto 0));

end dead_generator;

architecture gen of dead_generator is

begin

process(clk)

begin

if(clk'event and clk = '1') then

if((pa = '1') and (count/= dead_time)) then

count