选择合适的系列电压基准源的绝对精度电压输出
Load-Regulation Error = 140µA × 6ppm / mA ~= 1ppm (max)The power supply is specified as being constant in this application, so the line regulation is assumed to be 0ppm. Note that it would be 1ppm even if the power supply weren't constant, as long as it remained within the specified 4.95V to 5.05V range, because the MAX6325 line-regulation specification is 7ppm/V max.
Because the bandwidth for Design B is specified as DC to 1kHz, we need to consider both the 1.5µVp-p low-frequency (1/f) noise and the 2.8µVRMS broadband noise specified from 0.1Hz to 10Hz and 10Hz to 1kHz, respectively. Using the same crude RMS to peak approximation as Design A, and adding the two peak noise terms together, we get a total noise estimate of 2ppm at the reference output ([[0.75µV + 2.8µVRMS × √2]/2.5V] × 106). Notice that this is the same value we would obtain if we calculated it at the DAC output, because the equation would be multiplied by 1.638/1.638 to rescale everything to 4.096V. It's worth mentioning that the peak-noise-sum method used here is fairly conservative, yet the total error contribution is still relatively small. An RSS approach is probably more accurate, because the two noise sources are most likely uncorrelated, but this smaller value would be even more "in the noise" (pun intended) compared to the peak-value approach.
All that remains for the Design-B analysis is to include the DAC error terms. The INL for the A-grade MAX5170 DAC is specified as ±1LSB, which is 61ppm and exactly half of our 122ppm error budget of ±2LSB at 14 bits. The DAC gain error is specified as ±8LSB worst-case, but this error is removed completely by the gain calibration mentioned earlier. The calibration works as follows: The DAC is set to a digital code where the ideal output voltage is known (for example, decimal DAC code 16380 should produce precisely 4.095V at the output). The reference voltage is then trimmed until the DAC output voltage is at this exact value, even if the reference voltage itself is not 2.500V. The MAX5170 DAC does not list a gain tempco, although the gain error is specified over the operating-temperature range. Because the gain error is calibrated out at only one temperature, Design B should be tested to ensure that the gain does not drift excessively over temperature. The final consideration is the MAX5170 DAC output noise, whose typical peak noise is roughly estimated as 1ppm ([106 × √(1000Hz × π/2) × 80nVRMS/√Hz × √2]/4.096V).
In the end, the final worst-case accuracy is 184ppm (~ ±3LSB at 14 bits), which doesn't quite meet our accuracy target of 122ppm, whereas the RSS accuracy is acceptable at 100ppm. Based on these numbers, we consider the design a success, because it has illustrated the important points and is close to the target accuracy with several conservative assumptions. In a real-world application, this design could be accepted as is, or the accuracy requirements could be loosened slightly. Alternatively, a more expensive reference could be used if this design were not acceptable.
Design C: One-Time Calibrated, Low Drift
The initial error of the A-grade MAX6162 is 0.1%, which consumes the entire Design-C error budget of 977ppm. However, like Design B, this is (at least partially) calibrated out. Note that the uncalibrated +4.096V MAX5154 DAC full-scale output voltage exceeds the required +4.000V output range, and the DAC has 1mV resolution even though only ±4mV of accuracy is required. Therefore, it is possible to do a "digital calibration" on the DAC input digital codes to remove some of the reference's initial error and the DAC's gain error.The digital gain calibration is best demonstrated with an example: Assume the DAC output voltage needs to be at the full-scale value of 4.000V, but the ideal decimal DAC code of 4000 results in a measured output of only 3.997V due to various errors in the system. Using digital calibration, a correction value is added to the DAC code to produce the desired result. In this example, when the DAC output voltage of 4.000V is required, a corrected DAC code of 4003 is used instead of 4000. This gain calibration is scaled linearly across the DAC codes, so it has little effect at the lower codes and more impact on the upper codes.
The digital gain calibration accuracy is limited by the 12-bit resolution of the DAC, so the best we can hope for is ~ ±1mV or 244ppm (106 × 1mV/4.096V) of error after the calibration has been applied. Note that the accuracy is calculated on a 4.096V scale in this example to maintain consistency, but it could be calculated relative to the +4.000V output range if required by the application, and the error would be slightly higher.
If the required output range in this example were 4.096V, there are other options that could be used to always bias the uncalibrated DAC output voltage above 4.096V, so that the digital gain calibration scheme described in this example could be employed. Such options include the following:
- Using an adjustable reference whose output is always above 4.096V when all circuit tolerances are considered
- Using a force/sense DAC with the gain set slightly higher than necessary
- Adding an output buffer with gain
We find Design C's worst-case reference output current variation to be 293µA (2.5V/[14kΩ||14kΩ], remember there are two DACs driven by the reference), which is used directly in the load-regulation calculation:
| Load-Regulation Error | = 293µA × 0.9mV / mA = 264µV (max) |
| = 106 × 264µV / 2.048V = 129ppm (max) |
Because reference-load regulation is proportional to the reference output voltage, it can be calculated at either the voltage reference (264µV/2.048V) or the DAC output ((2 × 264µV)/(2 × 2.048V)).
The power supply is constant in this application, so the line regulation is assumed to be 0ppm. With the bandwidth for Design C specified as 0.1Hz to 10Hz, we use half of the 22µVp-p low-frequency (1/f) noise specification (peak value) to arrive at a noise contribution of 5ppm at the reference output (106 × (22µV/2)/2.048V)). As mentioned previously, we get the same 5ppm answer if the calculation is referred to the DAC output, because the equation is just multiplied by 2.0/2.0.
Moving on to the MAX5154 DAC error terms, the A-grade INL is ±0.5LSB, which is 122ppm on the 12-bit scale. The DAC gain error is ±3LSB(244ppm), but it is ignored because it was already accounted for in the digital reference/DAC gain calibration mentioned earlier in this step and we don't want to count it twice. The MAX5154 gain-error tempco has a typical value of 4ppm/°C, which gives us a total of 500ppm (125°C × 4ppm/°C). The DAC output noise is not specified for the MAX5154, so it is ignored. We recognize that this could present a problem, but our experience with Design B indicates that DAC noise is usually a relatively small contributor to the total error. Measurements can be performed to confirm this assumption.
The worst-case error for Design C is calculated as 1865ppm, and the RSS error is 874ppm. With a target-error specification of 977ppm, the current design is marginally acceptable at best, especially given that some typical values were used and the DAC output noise was not considered. The details of Design C will not be rehashed here, because the important points have already been covered. However, some options for improvement are as follows:
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