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设计基于LED的视频显示板,Designing an LED

作者： 时间：2011-12-24 来源：网络 收藏
livered in sequence from left to right on each line and from the top to bottom on each frame through the TFP401A DVI receiver. The MAX6974's individual PWM frame format requires the same color information for a group of eight pixels to be delivered together (Table 1). A buffer is needed to hold at least eight pixels of data for this format conversion. A buffer for the entire video frame is used for the reference design, taking into account the adjacent line and blanking overhead removal, while maintaining an almost constant data delivery rate through the LVDS channels. The buffering also enables the interconnection of multiple MAX6974 devices at both ends of a PCB, thus avoiding long LVDS links from right to left ends.

Table 1. MAX6974 Individual PWM Data Frame Format
HEADER DATA 1 DATA 2 DATA 3 ... DATA N
HDR[23:0] B7, B6, ...R0 B7, B6, ...R0 B7, B6, ...R0 ... B7...R0
B_...G_...R_ 12-bit (MAX6974) or 14-bit (MAX6975) data each

Besides delivering the individual port PWM information, three other data frames with header CMD bits of 010101, 101010, and 111111 are used to deliver CALDAC, global intensity PDM, and configuration information through the MAX6974's LVDS interface (Table 2). Each header consists of 24 bits. The first byte is the same synchronization pattern of 11101000, followed by six CMD bits, and then ten counter (CNTR) bits. The CMD bits for the individual port PWM data frame is 000000.

Table 2. MAX6974 Data Frame Header Format
HDR
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC
CMD
CNTR
7 6 5 4 3 2 1 0 1 0 1 0 1 0 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 0 0 0
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关键词：LED视频显示板

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