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这个作业没有完全按照51FPGA的要求做，之前一直想能控制，
功能：实现3位拨码开关控制LED的样式，包含闪烁灯，流水灯以及花样灯（花样灯参考有51的程序）
视屏：


视频地址：http://union.bokecc.com/flash/player.swf?vid=6BC2B1CD78955E89&siteid=290666218ACBA694&playerid=EEA982EE6B20F4D1&playertype=1
代码如下：
module led_z(clk,
rst_n,
LED,
SW);
input clk; //50MHZ
input rst_n; //系统复位，低电平有效
input [2:0]SW; //3位拨码开关输入
output[7:0] LED; //8位LED_R输出
reg[7:0] LED_R; //8位LED_R输出寄存器
reg[24:0] delay; //LED_R计数器
//-----------------------------------
reg [7:0] flicker;
reg [7:0] run;
reg [7:0] water;
reg [4:0] state;

//--------------延时计数器-------------------------
always @(posedge clk or negedge rst_n)
if(!rst_n) delay<=25'd0;
else if(delay==25'd24999999)
begin
delay<=25'd0;
end
else begin
delay<=delay+1'd1;
end
//---------------流水灯程序-------------------------
always @(posedge clk or negedge rst_n)
if(!rst_n) water <= 8'b0;
else if(delay==25'd2499999)
begin
case(state)
5'b00000: water=8'b11111111;
5'b00001: water=8'b00000000;
5'b00010: water=8'b10000000;
5'b00011: water=8'b11000000;
5'b00100: water=8'b11100000;
5'b00101: water=8'b11110000;
5'b00110: water=8'b11111000;
5'b00111: water=8'b11111100;
5'b01000: water=8'b11111110;
5'b01001: water=8'b11111111;
5'b01010: water=8'b00000000;
5'b01011: water=8'b11111111;
5'b01100: water=8'b00000001;
5'b01101: water=8'b00000010;
5'b01110: water=8'b00000100;
5'b01111: water=8'b00001000;
5'b10000: water=8'b00010000;
5'b10001: water=8'b00100000;
5'b10010: water=8'b01000000;
5'b10011: water=8'b10000000;
5'b10100: water=8'b11111111;
5'b10101: water=8'b00000000;
5'b10110: water=8'b11111111;
5'b10111: water=8'b10000001;
5'b11000: water=8'b11000011;
5'b11001: water=8'b11100111;
5'b11010: water=8'b11111111;
5'b11011: water=8'b00011000;
5'b11100: water=8'b00111100;
5'b11101: water=8'b01111110;
5'b11110: water=8'b11111111;
5'b11111: water=8'b00000000;
endcase
state=state+1;
end
//-------------跑马灯程序---------------------

always @(posedge clk or negedge rst_n)
if(!rst_n) run<=8'h7f;
else
begin
if(delay==25'd2499999)
run<={run[0],run[7:1]};
else
run<=run;
end

//----------------闪烁灯程序----------------------
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) flicker <= 8'hff;
else
begin
if(delay == 25'd249999)
flicker <= ~flicker;
else
flicker <= flicker;
end
end
//----------------LED控制--------------------------
always @(posedge clk)
begin
case(SW[2:0])
3'b0: LED_R<=8'hff;
3'b001: LED_R<=flicker;
3'b010: LED_R<=run;
3'b100: LED_R<=water;
endcase
end
assign LED=LED_R;
endmodule

这些作业之前已经编好，今天一次性上传,工作比较忙，所以有些简单的就没写注释
功能：实现八位拨码开关，控制数码管显示0到8。
视频如下：

代码如下：
module led_display(clk,
rst_n,
SEG,
DIG,
SW);
input clk; //50MHZ
input rst_n; //系统复位，低电平有效
input[7:0] SW; //8位拨码开关输入
output[7:0] SEG; //段选
output[7:0] DIG; //位选
//wire[7:0] data;
reg[7:0] SEG; //
wire[7:0] DIG; //

//-------------------------------------
always@(posedgeclk or negedge rst_n)
begin
case(SW)
8'b0: SEG=8'hc0; //0
8'b00000001: SEG=8'hf9; //1
8'b00000010: SEG=8'ha4; //2
8'b00000100: SEG=8'hb0; //3
8'b00001000: SEG=8'h99; //4
8'b00010000: SEG=8'h92; //5
8'b00100000: SEG=8'h82; //6
8'b01000000: SEG=8'hf8; //7
8'b10000000: SEG=8'h80; //8
/*4'h9: SEG=8'h90; //9
4'ha: SEG=8'h88; //a
4'hb: SEG=8'h83; //b
4'hc: SEG=8'hc6; //c
4'hd: SEG=8'ha1; //d
4'he: SEG=8'h86; //e
4'hf: SEG=8'h8e; //f*/
endcase
end
assign DIG=8'b0;
endmodule

这些作业之前已经编好，今天一次性上传,工作比较忙，所以有些简单的就没写注释
功能：显示一个模为60的计数器，即显示从0到59。
视频如下：


视频地址：http://union.bokecc.com/flash/player.swf?vid=592C7C1D59EEBA3A&siteid=290666218ACBA694&playerid=EEA982EE6B20F4D1&playertype=1
代码如下：
module led_scan(clk,
rst_n,
SEG,
DIG);
input clk; //50MHZ
input rst_n; //系统复位，低电平有效
output[7:0] SEG; //段选
output[7:0] DIG; //位选
reg[7:0] SEG; //段选寄输出存器
reg[7:0] DIG; //段选寄输出存器
reg[3:0] num_ge; //个位寄存器
reg[3:0] num_shi; //十位寄存器
reg[7:0] SSEG; //个位寄存器
reg[7:0] GSEG; //十位寄存器
reg cnt; //个十位选
reg[25:0] delay; //计数器
reg[14:0] delay_1k; //刷新频率1KHZ
reg delay_1s; //1S计数器
//-------------------------------------
initial
begin
num_ge<=4'd0;
num_shi<=3'd0;
cnt<=1'b0;
end
always @(posedge clk or negedge rst_n)
if(!rst_n) delay<=26'd0;
else
begin
if(delay==26'd24999999)
begin
delay_1s<=~delay_1s;
delay<=26'd0;
end
else
begin
delay<=delay+1'b1;
end
end
always @(posedge clk or negedge rst_n)
if(!rst_n) delay_1k<=15'd0;
else
if(delay_1k==15'd4999)
begin
cnt<=~cnt;
delay_1k<=15'd0;
end
else
delay_1k<=delay_1k+1'b1;
//---------------------------------------------------
always@(posedgedelay_1s or negedge rst_n)
if(!rst_n) begin
num_ge<=4'd0;
num_shi<=3'd0;
end
else
begin
if(num_ge==4'd9&&num_shi<3'd5)
begin
num_ge<=4'd0;
num_shi<=num_shi+3'd1;
end
else if(num_ge==4'd9&&num_shi==3'd5)
begin
num_ge<=4'd0;
num_shi<=3'd0;
end
else
begin
num_ge<=num_ge+4'd1;
end
end
//-----------------------------------

always@(num_ge)
begin
case(num_ge)
4'd0 : SSEG = 8'hc0; // "0"
4'd1 : SSEG = 8'hf9; // "1"
4'd2 : SSEG = 8'ha4; // "2"
4'd3 : SSEG = 8'hb0; // "3"
4'd4 : SSEG = 8'h99; // "4"
4'd5 : SSEG = 8'h92; // "5"
4'd6 : SSEG = 8'h82; // "6"
4'd7 : SSEG = 8'hf8; // "7"
4'd8 : SSEG = 8'h80; // "8"
4'd9 : SSEG = 8'h90; // "9"
endcase
end
always@(num_shi)
begin
case(num_shi)
3'd0 : GSEG = 8'hc0; // "0"
3'd1 : GSEG = 8'hf9; // "1"
3'd2 : GSEG = 8'ha4; // "2"
3'd3 : GSEG = 8'hb0; // "3"
3'd4 : GSEG = 8'h99; // "4"
3'd5 : GSEG = 8'h92; // "5"
3'd6 : GSEG = 8'h82; // "6"
/*3'd7 : GSEG = 8'hf8; // "7"
3'd8 : GSEG = 8'h80; // "8"
3'd9 : GSEG = 8'h90; // "9"*/
endcase
end
always@(cnt)
begin
if(cnt) begin
SEG<=GSEG;
DIG<=8'hfd;
end
if(!cnt) begin
SEG<=SSEG;
DIG<=8'hfe;
end
end
endmodule