让我也来试试
moduleADC_Select(inputCLK,inputReset_n,outputregF_S_CLK_0,outputregF_S_CLK_SELF);//if F_S_CLK_0 = 1, ALL ADC has the same CLK from PLL_0; //if F_S_CLk_SELF =1,ADC's CLKs are from different PLL, //forexample PLL1,PLL2,PLL3,PLL4,PLL5,PLL6,PLL7,PLL8always@(posedgeCLKornegedgeReset_n)if(!Reset_n)beginF_S_CLK_0<=1'b1;F_S_CLK_SELF<=1'b0;endelsebeginF_S_CLK_0<=1'b1;F_S_CLK_SELF<=1'b0;endendmodule