EEPW论坛

module dianzi(sys_clk,sys_rst,sm_seg,sm_bit);
//输入/输出信号
input sys_clk;
input sys_rst;
output [7:0] sm_seg;
output [7:0] sm_bit;

reg [7:0] sm_seg;
reg [7:0] sm_bit;
reg [3:0] sl;
reg [3:0] sh;
reg [3:0] sml;
reg [3:0] smh;
reg cn1;
reg cn2;
reg [25:0] miao_cnt;
reg [5:0] miao;
reg [2:0] disp_dat;
reg [4:0] dataout_buf ;
reg [15:0] delay_cnt ;

always@(posedgesys_clk or negedge sys_rst)
begin
if(!sys_rst)
miao_cnt<=26'd0;
else
begin
if(miao_cnt==26'd49999999)
miao_cnt<=26'd0;
else
miao_cnt<=miao_cnt+1'd1;
end
end
always@(posedgesys_clk or negedge sys_rst)
begin
if(!sys_rst)
{sh,sl}<=8'h00;
else
begin
if(miao_cnt==26'd49999999)
begin
if (sl==4'd9)
begin
sl<=4'd0;
if(sh==5)
begin
sh<=4'd0;
cn1<=1'd1;
end
else
sh<=sh+1;
end
else
sl<=sl+1'd1;
end
else
sl<=sl;
end
end
always@(cn1)
begin
if(cn1==1)
begin
if (sml==4'd9)
begin
sml<=4'd0;
if(smh==5)
begin
smh<=4'd0;
cn2<=1;
end
else
begin
smh<=smh+1;
cn1<=1'd0;
end
end
else
begin
sml<=sml+1'd1;
cn1<=1'd0;
end
end
else
sml<=sml;
end

always@(posedgesys_clk or negedge sys_rst)
begin
if(!sys_rst)
delay_cnt<=16'd0;
else
begin
if(delay_cnt==16'd49999)
delay_cnt<=16'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedgesys_clk or negedge sys_rst)
begin
if(!sys_rst)
disp_dat<=4'd0;
else
begin
if(delay_cnt==16'd49999)
disp_dat<=disp_dat+1'b1;
else
disp_dat<=disp_dat;
end
end
always @(disp_dat)
begin
case(disp_dat)
3'b000 :
sm_bit = 8'b1111_1110;
3'b001 :
sm_bit = 8'b1111_1101;
3'b010 :
sm_bit = 8'b1111_1011;
3'b011 :
sm_bit = 8'b1111_0111;
3'b100 :
sm_bit = 8'b1110_1111;
default :
sm_bit = 8'b1111_1111;
endcase
end

always@(sm_bit)
begin
case(sm_bit)
8'b1111_1110:
case(sl)
4'h0 : dataout_buf = 0;
4'h1 : dataout_buf = 1;
4'h2 : dataout_buf = 2;
4'h3 : dataout_buf = 3;
4'h4 : dataout_buf = 4;
4'h5 : dataout_buf = 5;
4'h6 : dataout_buf = 6;
4'h7 : dataout_buf = 7;
4'h8 : dataout_buf = 8;
4'h9 : dataout_buf = 9;
endcase
8'b1111_1101:
case(sh)
4'h0 : dataout_buf = 0;
4'h1 : dataout_buf = 1;
4'h2 : dataout_buf = 2;
4'h3 : dataout_buf = 3;
4'h4 : dataout_buf = 4;
4'h5 : dataout_buf = 5;
4'h6 : dataout_buf = 6;
4'h7 : dataout_buf = 7;
4'h8 : dataout_buf = 8;
4'h9 : dataout_buf = 9;
endcase
8'b1111_1011:
dataout_buf = 10;
8'b1111_0111:
case(sml)
4'h0 : dataout_buf = 0;
4'h1 : dataout_buf = 1;
4'h2 : dataout_buf = 2;
4'h3 : dataout_buf = 3;
4'h4 : dataout_buf = 4;
4'h5 : dataout_buf = 5;
4'h6 : dataout_buf = 6;
4'h7 : dataout_buf = 7;
4'h8 : dataout_buf = 8;
4'h9 : dataout_buf = 9;
endcase
8'b1110_1111:
case(smh)
4'h0 : dataout_buf = 0;
4'h1 : dataout_buf = 1;
4'h2 : dataout_buf = 2;
4'h3 : dataout_buf = 3;
4'h4 : dataout_buf = 4;
4'h5 : dataout_buf = 5;
4'h6 : dataout_buf = 6;
4'h7 : dataout_buf = 7;
4'h8 : dataout_buf = 8;
4'h9 : dataout_buf = 9;
endcase
default:
dataout_buf=0;
endcase
end

always@(dataout_buf)
begin
case(dataout_buf)
4'h0 : sm_seg = 8'hc0; // "0"
4'h1 : sm_seg = 8'hf9; // "1"
4'h2 : sm_seg = 8'ha4; // "2"
4'h3 : sm_seg = 8'hb0; // "3"
4'h4 : sm_seg = 8'h99; // "4"
4'h5 : sm_seg = 8'h92; // "5"
4'h6 : sm_seg = 8'h82; // "6"
4'h7 : sm_seg = 8'hf8; // "7"
4'h8 : sm_seg = 8'h80; // "8"
4'h9 : sm_seg = 8'h90; // "9"
default :
sm_seg = 8'hbf; // "-"
endcase
end
endmodule

我做的是电子钟

Error (10028): Can't resolve multiple constant drivers for net "cn1" at dianzi.v(40)

请问这个是什么错误？