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单独驱动tlc5615时有效，但是放入其他工程时就不能输入想要的电压，只输出固定的0.62V

module spidac(clk, Reset, dac_sclk, DAC_nCS, dac_din,led,led2);
input clk;
input Reset;
output dac_sclk;
output DAC_nCS;
output dac_din;
output led;
output led2;

reg [11:0] shift_reg;
reg [11:0] DAC_HIGH = 12'b111111111100;
reg [11:0] DAC_LOW = 12'b111111111100;
reg loadH;

reg [3:0] state;

parameter [3:0] IDLE = 4'b0010;
parameter [3:0] LOAD = 4'b0110;
parameter [3:0] CSDAC = 4'b0000;
parameter [3:0] TxD0 = 4'b0001;
parameter [3:0] TxD1 = 4'b0101;
parameter [3:0] TXD2 = 4'b0100;
parameter [3:0] shift = 4'b1000;
parameter [3:0] spiend1 = 4'b1100;
parameter [3:0] spiend2 = 4'b1010;

reg wait_on;
reg [2:0] wait_cnt;

reg clkdiv2;
reg clkdiv4;

reg [3:0] bit_cnt;
reg led_r;
reg led_r2;
reg[14:0] cs_cnt;

always @(posedge clk or negedge Reset)
if (Reset == 1'b0)
clkdiv2 <= 1'b0;
else
clkdiv2 <= (~clkdiv2);


always @(posedge clkdiv2 or negedge Reset)
if (Reset == 1'b0)
clkdiv4 <= 1'b0;
else
clkdiv4 <= (~clkdiv4);


always @(negedge Reset or posedge clkdiv4)
begin: xhdl0
integer i;
if (Reset == 1'b0)
begin
bit_cnt <= 4'b0000;
state <= IDLE;
loadH <= 1'b1;
wait_on <= 1'b0;
end
else
case (state)
IDLE :
state <= LOAD;
LOAD :
begin
state <= CSDAC;
bit_cnt <= 4'b0000;
if (loadH == 1'b1)
shift_reg <= DAC_HIGH;
else
shift_reg <= DAC_LOW;
end
CSDAC :
state <= TxD0;
TxD0 :
begin
state <= TxD1;
bit_cnt <= bit_cnt + 1;

end
TxD1 :
state <= shift;
shift :
begin
state <= TXD2;
for (i = 11; i >= 1; i = i - 1)
shift_reg[i] <= shift_reg[i - 1];

shift_reg[0] <= 1'b0;
end
TXD2 :
if (bit_cnt == 4'b1100)
state <= spiend1;
else
state <= TxD0;
spiend1 :
begin
state <= spiend2;
wait_on <= 1'b1;
end
spiend2 :
if (wait_cnt == 3'b111)
begin
state <= LOAD;
wait_on <= 1'b0;
loadH <= (~loadH);
led_r <= (~led_r);
end
default :
state <= IDLE;
endcase
end


always @(negedge Reset or negedge clkdiv4)
if (Reset == 1'b0)
wait_cnt <= 3'b000;
else
begin
if (wait_on == 1'b1)
wait_cnt <= wait_cnt + 1;

else
wait_cnt <= 3'b000;
led_r2<=~led_r2;
end

always @(posedge state[1] or negedge Reset)
if (Reset == 1'b0)
cs_cnt <= 15'd0;
else
begin
if (cs_cnt == 15'd5)
begin
cs_cnt <= 15'd0;
DAC_HIGH <= DAC_HIGH + 12'b000000000100;
DAC_LOW <= DAC_LOW + 12'b000000000100;
end
else
cs_cnt <= cs_cnt+1;


end


assign dac_din = shift_reg[11];
assign dac_sclk = state[0];
assign DAC_nCS = state[1];
assign led=led_r;
assign led2=led_r2;
endmodule