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A linearization technique for RF low noise amplifierA LINEARIZATION TECHNIQUE FOR RF LOW NOISE AMPLIFIER Chunyu Xin, Edgar S anchez-Sinencio Texas A&M University Department of Electrical Engineering College Station, TX 77843
ABSTRACT A LNA linearization technique derived from multi-gated conguration using bipolar transistors in CMOS technology is proposed. Bipolar transistor is used to replace the auxiliary MOS transistor to achieve higher operational speed. Both single-ended and differential applications are investigated. Simulation shows that this method is competitive with already reported low noise ampliers . For 3GHz of frequency operation, the single-ended structure achieves +15dBm IIP3 with 8.9mW power consumption, and the differential architecture can achieve +14dBm IIP3 with 21mW power consumption. 1. INTRODUCTION Linearity is a ke
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