静态数码管

静态数码管

/*--------------------------------------------------------
-- Engineer: zhrscut
-- Create Date:
-- Module Name:
-- Tool Versions: Quartus_II 9.1
-- 欢迎加入 EEPW ，FPGA 开发板 DIY 活动
--------------------------------------------------------*/
/*--------------------------------------------------------
-- Engineer: zhrscut
-- Create Date:
-- Module Name:
-- Tool Versions: Quartus_II 9.1
-- -EEPWFPGA°DIY
--------------------------------------------------------*/
module static_segled(clk,rst_n,sel,data);

input clk;
input rst_n;
output[7:0] sel;
output[7:0] data;

reg[7:0] data;
wire[7:0] sel;
reg[3:0] num;
reg[28:0] cnt;

assign sel=8'b0000_0000;


always @(posedge clk or negedge rst_n)
if(!rst_n) cnt<=29'd0;
else cnt<=cnt+1;

always @(cnt[25])
begin
num={cnt[28:25]};
end

//-