器件名称:
DM74LS109AN
功能描述:
Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
文件大小:
52.33KB 共5页
简 介:
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs June 1986 Revised March 2000 DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the J and K inputs may be changed while the clock is HIGH or LOW as long as setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number DM74LS109AM DM74LS109AN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs PR L H L H H H H H CLR H L L H H H H H CLK X X X ↑ ↑ ↑ ↑ L J X X X L H L H X K X X X L L H H X Q0 H Q0 Q H L L Toggle Q0 L Q0 Outputs Q L H H H (Note 1) H (Note 1) H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↑ = Rising Edge of Pulse Q0 = The output l……
