器件名称:
CD54AC109
功能描述:
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
文件大小:
346.39KB 共12页
简 介:
CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE (TOP VIEW) 1CLR 1J 1K 1CLK 1PRE 1Q 1Q GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC 2CLR 2J 2K 2CLK 2PRE 2Q 2Q description/ordering information The ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. ORDERING I……
