器件名称:
CD54AC113A
功能描述:
Dual
文件大小:
10.3KB 共1页
简 介:
S E M I C O N D U C T O R CD54AC112/3A CD54ACT112/3A Dual “J-K” Flip-Flop with Set and Reset Functional Diagram 1S 1J 1K 1CP 1R 2S 2J 2K 2CP 4 3 2 1 15 10 11 12 13 14 GND = 8 VCC = 16 FF 2 FF 1 June 1997 COMPLETE DATA SHEET COMING SOON! Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” ip-ops with set and reset that utilize the Harris Advanced CMOS Logic technology. These ip-ops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC112/3A and CD54ACT112/3A changes state on the negative-going transition of the clock. Set and Reset are accomplished asynchronously by low-level inputs. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F sufx). ACT INPUT LOAD TABLE INPUT J, CP, CP K S, R NOTE: 1. Unit load is ICC limit specied in DC Electrical Specications Table, e.g., 2.4mA Max at +25oC. UNIT LOAD (NOTE 1) 1 0.53 5 1Q 6 1Q 9 2Q 7 2Q 2R 0.58 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current, Per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or GND Current, ICC or IGND For Up to 4 Outputs Per Device, Add ±25mA For Each Additional O……
