器件名称:
CD54AC74
功能描述:
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
文件大小:
330.9KB 共6页
简 介:
CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCHS231D – SEPTEMBER 1998 – REVISED DECEMBER 2002 D D D D D D AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54AC74 . . . F PACKAGE CD74AC74 . . . E OR M PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q description/ordering information The ’AC74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION TA PDIP – E 55°C to 125°C –55 SOIC – M PACKAGE Tube Tube Tape and reel ORDERABLE PART NUMBER CD74AC74E CD74AC74M CD74AC74M96 TOP-SIDE MARKING CD74AC74E AC74M CDIP – F Tube CD5……
