器件名称:
CD54HC112_08
功能描述:
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
文件大小:
643.79KB 共18页
简 介:
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H March 1998 - Revised October 2003 Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger Description The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These ip-ops have independent J, K, Set, Reset, and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs. The HCT logic family is functionally as well as pincompatible with the standard LS logic family. . Features [ /Title (CD74 HC112 , CD74 HCT11 2) /Subject (Dual J-K FlipFlop with Set and Reset Nega Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Set and Reset Complementary Outputs Buffered Inputs Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC =……
