器件名称:
CD54HC160
功能描述:
BCD SYNCHRONOUS DECADE COUNTERS
文件大小:
248.74KB 共14页
简 介:
CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 D D D D D D D D Synchronous Counting and Loading Two Count-Enable Inputs for n-Bit Cascading Asynchronous Reset (CD54HC160) Synchronous Reset (CD54HC162) Look-Ahead Carry for High-Speed Counting Operating Range 2-V to 6-V VCC EPIC (Enhanced-Performance Implanted CMOS) Process Packaged in Ceramic (F) DIPs CD54HC160, CD54HC162 . . . F PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RCO QA QB QC QD ENT LOAD description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. Th……
