器件名称:
CD54HC173F
功能描述:
High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State
文件大小:
520.39KB 共20页
简 介:
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Data sheet acquired from Harris Semiconductor SCHS158E February 1998 - Revised October 2003 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State Description The ’HC173 and ’HCT173 high speed three-state quad Dtype ip-ops are fabricated with silicon gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky devices. The buffered outputs can drive 15 LSTTL loads. The large output drive capability and three-state feature make these parts ideally suited for interfacing with bus lines in bus oriented systems. The four D-type ip-ops operate synchronously from a common clock. The outputs are in the three-state mode when either of the two output disable pins are at the logic “1” level. The input ENABLES allow the ip-ops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic “1” level, the Q outputs are fed back to the inputs, forcing the ip-ops to remain in the same state. Reset is enabled by taking the MASTER RESET (MR) input to a logic “1” level. The data outputs change state on the positive going edge of the clock. The ’HCT173 logic family is functionally, as well as pin compatible with the standard LS logic family. Features Three-State Buffered Outputs [ /Title (CD74H C173, CD74H CT173) /Subject (High Speed CMOS Logic Quad DType Gated Input and ……
