器件名称:
CD54HC377F3A
功能描述:
High-Speed CMOS Logic Octal D-Type Flip-Flop With Data Enable
文件大小:
311.37KB 共13页
简 介:
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377 Data sheet acquired from Harris Semiconductor SCHS184C September 1997 - Revised February 2004 High-Speed CMOS Logic Octal D-Type Flip-Flop With Data Enable Description The ’HC377 and ’HCT377 are octal D-type ip-ops with a buffered clock (CP) common to all eight ip-ops. All the ipops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E) is Low. Features Buffered Common Clock [ /Title (CD74 HC377 , CD74 HCT37 7) /Subject (High Speed CMOS Logic Octal DType Flip- Buffered Inputs Typical Propagation Delay at CL = 15pF, VCC = 5V, TA = 25oC - 14 ns (HC Types - 16 ns (HCT Types) Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1A at VOL, VOH Ordering Information PART NUMBER CD54HC377F3A CD54HCT377F3A CD74HC377E CD74HC377M CD74HC377M96 CD74HC377PW CD74HC377PWR CD74HCT377E CD74HCT377M CD74HCT377M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 ……
