器件名称:
CD54HC4017
功能描述:
DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS
文件大小:
125.36KB 共9页
简 介:
CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 D D D D D D D D 2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V Packaged in Ceramic (F) DIP Package and Also Available in Chip Form (H) F PACKAGE (TOP VIEW) 5 1 0 2 6 7 3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC MR CP CE TC 9 4 8 description The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low. The CD54HC4017 is characterized for operation over the full military temperature range of –55°C to 125°C. FUNCTION TABLE INPUTS CP L X X ↑ ↓ X H CE X H X L X ↑ ↓ MR L L H L L L L OUTPUT STATE No change No change 0=H 1–9 = L Increments counter No change No change Increments counter If n < 5, TC = H; otherwise, TC = L. Please be aware that an important notice concerning availability, standard war……
