器件名称:
CD54HCT109
功能描述:
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger
文件大小:
279.59KB 共12页
简 介:
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger Description The ’HC109 and ’HCT109 are dual J-K ip-ops with set and reset. The ip-op changes state with the positive transition of Clock (1CP and 2CP). The ip-op is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. Features Asynchronous Set and Reset [ /Title (CD74H C109, CD74H CT109) /Subject (Dual JK FlipFlop with Set and Reset Schmitt Trigger Clock Inputs Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1A at VOL, VOH Ordering Information PART NUMBER CD54HC109F3A CD54HCT109F3A CD74HC109E CD74HC109M CD74HC109MT CD74HC109M96 CD74HCT109E……
