器件名称:
CD54HCT125F3A
功能描述:
High-Speed CMOS Logic Quad Buffer, Three-State
文件大小:
265.02KB 共12页
简 介:
CD54HC125, CD74HC125, CD54HCT125, CD74HCT125 Data sheet acquired from Harris Semiconductor SCHS143C November 1997 - Revised August 2003 High-Speed CMOS Logic Quad Buffer, Three-State Description The ’HC125 and ’HCT125 contain 4 independent three-state buffers, each having its own output enable input, which when “HIGH” puts the output in the high impedance state. Features Three-State Outputs [ /Title (CD74 HC125 , CD74 HCT12 5) /Subject (High Speed CMOS Logic Quad Buffer, ThreeState) Separate Output Enable Inputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1A at VOL, VOH Ordering Information PART NUMBER CD54HC125F3A CD54HCT125F3A CD74HC125E CD74HC125M CD74HC125MT CD74HC125M96 CD74HCT125E CD74HCT125M CD74HCT125MT CD74HCT125M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SO……
