器件名称:
CD54HCT163F3A
功能描述:
High-Speed CMOS Logic Presettable Counters
文件大小:
285.95KB 共16页
简 介:
The CD54HCT161 is obsolete and no longer is supplied. Data sheet acquired from Harris Semiconductor SCHS154D CD54/74HC161, CD54/74HCT161, CD54/74HC163, CD54/74HCT163 High-Speed CMOS Logic Presettable Counters Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the ’HC161 and ’HCT161 types). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. The look-ahead carry feature simplifies serial cascading of the counters. Both count enable inputs (PE and TE) must be high to count. The TE input is gated with the Q outputs of all four stages so that at the maximum count the terminal count (TC) output goes high for one clock period. This TC pulse is used to enable the next cascaded stage. February 1998 - Revised October 2003 Features [ /Title (CD74 HC161 , CD74 HCT16 1, CD74 HC163 , CD74 HCT16 3) /Subject (High Speed CMOS Logic Presettable Counte rs) /Autho r () /Keywords (High Speed CMOS Logic Presettable Counte rs, High Speed ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset Synchronous Counting and Loading Two Count Enable Inputs for n-Bit Cascading Look-Ahead Carry for High-Speed Counting Fanout (Over Temperature Range) - Standard Outputs . . .……
