器件名称:
CD54HCT175
功能描述:
High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset
文件大小:
562.42KB 共15页
简 介:
CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Data sheet acquired from Harris Semiconductor SCHS160C August 1997 - Revised October 2003 High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q outputs to a logic 1. Features [ /Title (CD74 HC175 , CD74 HCT17 5) /Subject (High Speed CMOS Logic Quad DType Flip Common Clock and Asynchronous Reset on Four D-Type Flip-Flops Positive Edge Pulse Triggering Complementary Outputs Buffered Inputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1A at VOL, VOH Ordering Information PART NUMBER CD54HC175F3A CD54HCT175F3A CD74HC175E CD74HC175M CD74HC……
