器件名称:
CD54HCT390
功能描述:
High-Speed CMOS Logic Dual Decade Ripple Counter
文件大小:
423.68KB 共15页
简 介:
CD74HC390, CD54HCT390, CD74HCT390 Data sheet acquired from Harris Semiconductor SCHS185C September 1997 - Revised October 2003 High-Speed CMOS Logic Dual Decade Ripple Counter Description The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divideby-5 sections. These sections are normally used in a BCD decade or bi-quinary conguration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting congurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section. For bi-quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. The master reset inputs (1MR and 2MR) are active-High asynchronous inputs to each decade counter which operates on the portion of the counter identied by the “1” and “2” prexes in the pin conguration. A High level on the nMR input overrides the clock a……
