器件名称:
M74HC175
功能描述:
QUAD D-TYPE FLIP FLOP WITH CLEAR
文件大小:
428.39KB 共11页
简 介:
M74HC175 QUAD D-TYPE FLIP FLOP WITH CLEAR s s s s s s s HIGH SPEED : tPD = 16 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 175 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC175B1R M74HC175M1R T&R M74HC175RM13TR M74HC175TTR DESCRIPTION The M74HC175 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. These four flip-flops are controlled by a clock input (CLOCK) and a clear input (CLEAR). The information data applied to the D inputs (1D to 4D) are transferred to the outputs (1Q to 4Q and 1Q to 4Q) on the positive-going edge of the clock pulse. The reset function is accomplished when the CLEAR input is low and all Q outputs are low regardless of other input conditions. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 M74HC175 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 7, 10, 15 3, 6, 11, 14 4, 5, 12, 13 9 8 16 SYMBOL CLEAR 1Q to 4Q 1Q to 4Q 1D to 4D CLOCK GND Vcc NAME AND FUNCTION Asynchronous Master Reset (Active Low) Flip-Flop Outputs Complementary Flip-Flop Outputs Data Inputs Clock Input (LOW to HIGH, edge trigge……
