器件名称:
M74HC375B1R
功能描述:
QUAD D TYPE LATCH
文件大小:
245.42KB 共11页
简 介:
M54HC375 M74HC375 QUAD D TYPE LATCH . . . . . . . . HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS375 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC375F1R M74HC375M1R M74HC375B1R M74HC375C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC375 is a high speed CMOS QUAD D TYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOSlow power consumption. It contains two groups of 2-bit latches controlled by an enable input (G1 . 2 or G3 . 4). These two latch groups can be used in the different circuits. Each latch has Q and Q outputs (1Q to 4Q and 1Q to 4Q). The data applied to the data input is transferred to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input at that time is retained at the outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. February 1993 NC = No Internal Connection 1/11 M54/M……
