器件名称:
M74HC74M1R
功能描述:
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
文件大小:
453.58KB 共12页
简 介:
M74HC74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR s s s s s s s HIGH SPEED : fMAX = 67MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC74B1R M74HC74M1R T&R M74HC74RM13TR M74HC74TTR DESCRIPTION The M74HC74 is an high speed CMOS DUAL D TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. A signal on the D INPUT is transferred on the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low on the appropriate input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1,13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND Vcc NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW-to-HIGH, Edge-Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS CLR L H L H H H X : Don’t Care OUTPUTS FUNCTION D X X X L H X CK X X ……
