器件名称:
MC74AC74DTR2
功能描述:
Dual DType Positive EdgeTriggered FlipFlop
文件大小:
157.44KB 共12页
简 介:
MC74AC74, MC74ACT74 Dual DType Positive EdgeTriggered FlipFlop The MC74AC74/74ACT74 is a dual Dtype flipflop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features http://onsemi.com PDIP14 N SUFFIX CASE 646 1 14 1 14 SOIC14 D SUFFIX CASE 751A 14 1 TSSOP14 DT SUFFIX CASE 948G Outputs Source/Sink 24 mA ′ACT74 Has TTL Compatible Inputs PbFree Packages are Available VCC 14 CD2 13 D2 12 CP2 11 SD2 10 Q2 9 Q2 8 14 1 SOEIAJ14 M SUFFIX CASE 965 ORDERING INFORMATION D1 Q1 CP1 SD1 Q1 CD1 CP2 Q2 D 2 C D 2 Q2 SD2 See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. 1 CD1 2 D1 3 CP1 4 SD1 5 Q1 6 Q1 7 GND Figure 1. Pinout: 14Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 FUNCTION Data Inputs Clock……
