器件名称:
MC74ACT377M
功能描述:
Octal D Flip-Flop with Clock Enable
文件大小:
111.52KB 共12页
简 介:
MC74AC377, MC74ACT377 Octal D Flip-Flop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. http://onsemi.com PDIP–20 N SUFFIX CASE 738 20 1 Ideal for Addressable Register Applications Clock Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock Outputs Source/Sink 24 mA See MC74AC273 for Master Reset Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version ACT377 Has TTL Compatible Inputs MSL = 1 for all Surface Mount Chip Complexity: 292 FETS or 73 Gates 20 1 SO–20 DW SUFFIX CASE 751 20 1 TSSOP–20 DT SUFFIX CASE 948E 20 1 EIAJ–20 M SUFFIX CASE 967 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2001 1 May, 2001 – Rev.6 Publication Order Number: MC74AC37……
