器件名称: MC74HC273AF
功能描述: Octal D Flip-flop with Common clock and Reset with LSTTL-Compatible Inputs
文件大小: 155.42KB 共8页
简 介:MC74HCT273A Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT273A may be used as a level converter for interfacing TTL or NMOS outputs to High–Speed CMOS inputs. The HCT273A is identical in pinout to the LS273. This device consists of eight D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active low.
http://onsemi.com MARKING DIAGRAMS
20 PDIP–20 N SUFFIX CASE 738
1
MC74HCT273AN AWLYYWW 1 20
20
Output Drive Capability: 10 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 284 FETs or 71 Equivalent Gates
LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK 3 4 7 8 13 14 17 18 19 11 2 5 6 9 12 15 16 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
20 1
SOIC WIDE–20 DW SUFFIX CASE 751D 1 A WL YY WW
HCT273A AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week
PIN ASSIGNMENT
RESET Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND PIN 20 = VCC PIN 10 = GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK
RESET
1
FUNCTION TABLE
Inputs Reset L H H H H Clock X D X H L X X Output Q L H L No Change No Change
ORDERING INFORMATION
Device MC74HCT273AN MC74HCT273ADW Package PDIP–20 SOIC–WIDE Shi……
