器件名称:
MC74HC74ADT
功能描述:
Dual D Flip-Flop with Set and Reset
文件大小:
229.7KB 共7页
简 介:
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D Flip-Flop with Set and Reset High–Performance Silicon–Gate CMOS The MC54/74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information at a D–input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip–flop. The Set and Reset inputs are asynchronous. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 128 FETs or 32 Equivalent Gates MC54/74HC74A J SUFFIX CERAMIC PACKAGE CASE 632–08 1 14 14 1 N SUFFIX PLASTIC PACKAGE CASE 646–06 14 1 D SUFFIX SOIC PACKAGE CASE 751A–03 DT SUFFIX TSSOP PACKAGE CASE 948G–01 14 1 ORDERING INFORMATION MC54HCXXAJ MC74HCXXAN MC74HCXXAD MC74HCXXADT Ceramic Plastic SOIC TSSOP LOGIC DIAGRAM PIN ASSIGNMENT RESET 1 DATA 1 1 RESET 1 2 5 Q1 DATA 1 CLOCK 1 CLOCK 1 SET 1 RESET 2 DATA 2 3 4 13 GND 12 9 Q2 7 8 Q2 6 Q1 SET 1 Q1 Q1 1 2 3 4 5 6 14 13 12 11 10 9 VCC RESET 2 DATA 2 CLOCK 2 SET 2 Q2 CLOCK 2 SET 2 11 10 PIN 14 = VCC PIN 7 = GND 8 Q2 FUNCTION TABLE Inputs Set R……
