器件名称:
MC74HCT74AD
功能描述:
Dual D FlipFlop with Set and Reset with LSTTL Compatible Inputs
文件大小:
134.92KB 共6页
简 介:
MC74HCT74A Dual D FlipFlop with Set and Reset with LSTTL Compatible Inputs HighPerformance SiliconGate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flipflops with individual Set, Reset, and Clock inputs. Information at a Dinput is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flipflop. The Set and Reset inputs are asynchronous. Features http://onsemi.com MARKING DIAGRAMS 14 PDIP14 N SUFFIX CASE 646 1 14 14 1 SOIC14 D SUFFIX CASE 751A 1 A L, WL Y, YY W, WW G = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package HCT74AG AWLYWW MC74HCT74AN AWLYYWWG 14 1 Output Drive Capability: 10 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance With the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 136 FETs or 34 Equivalent Gates PbFree Packages are Available LOGIC DIAGRAM RESET 1 DATA 1 CLOCK 1 SET 1 RESET 2 DATA 2 CLOCK 2 SET 2 1 2 3 4 13 12 11 10 PIN 14 = VCC PIN 7 = GND 9 8 Q2 Q2 5 6 Q1 Q1 PIN ASSIGNMENT RESET 1 DATA 1 CLOCK 1 SET 1 Q1 Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RESET 2 DATA 2 CLOCK 2 SET 2 Q2 Q2 FUNCTION TABLE Inputs Set Reset Clock Data L H L H H H H H H L L H H H H H X X X X X……
