器件名称:
TDA10021HT
功能描述:
DVB-C channel receiver
文件大小:
92.74KB 共16页
简 介:
INTEGRATED CIRCUITS DATA SHEET TDA10021HT DVB-C channel receiver Product specication Supersedes data of 2000 Jun 21 File under Integrated Circuits, IC02 2001 Oct 01 Philips Semiconductors Product specication DVB-C channel receiver FEATURES 4, 16, 32, 64, 128 and 256 Quadrature Amplitude Modulation (QAM) demodulator (DVB-C compatible: ETS 300-429/ITU-T J83 annex A/C) High performance for 256 QAM, especially for direct IF applications On-chip 10-bit Analog-to-Digital Converter (ADC) On-chip Phase-Locked Loop (PLL) for crystal frequency multiplication (typically 4 MHz crystal) Digital downconversion Programmable half Nyquist filter (roll off = 0.15 or 0.13) Two Pulse Width Modulated (PWM) AGC outputs with programmable take over point (for tuner and downconverter control) Clock timing recovery, with programmable 2nd-order loop filter Variable symbol rate capability from SACLK/64 to SACLK/4 (SACLK = 36 MHz maximum) Programmable anti-aliasing filters Full digital carrier recovery loop Carrier acquisition range up to 18% of symbol rate Integrated adaptive equalizer (linear transversal equalizer or decision feedback equalizer) On-chip Forward Error Correction (FEC) decoder (de-interleaver and RS decoder) and fully DVB-C compliant DVB compatible differential decoding and mapping Parallel and serial transport stream interface simultaneously I2C-bus interface, for easy control CMOS 0.2 m technology. APPLICATIONS Cable set-top boxes Cable modems MMDS (ETS 300-7……
