器件名称:
EM484M3244VTA
功能描述:
128Mb (1M
文件大小:
678.93KB 共17页
简 介:
eorex Features Fully Synchronous to Positive Clock Edge Single 3.3V ±0.3V Power Supply LVTTL Compatible with Multiplexed Address Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page Programmable CAS Latency (C/L) - 2 or 3 Data Mask (DQM) for Read / Write Masking Programmable Wrap Sequence – Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) Burst Read with Single-bit Write Operation All Inputs are Sampled at the Rising Edge of the System Clock Auto Refresh and Self Refresh 4,096 Refresh Cycles / 64ms (15.625us) EM484M3244VTA 128Mb (1M×4Bank×32) Synchronous DRAM Description The EM484M3244VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 1Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL. Available packages:TSOPII 86P 400mil. Ordering Information Part No EM484M3244VTA-75F EM484M3244VTA-7F EM484M3244VTA-6F Organization 4M X 32 4M X 32 4M X 32 Max. Freq 133MHz @CL3 143MHz @CL3 166MHz @CL3 Package 86pin TSOP(ll) 86pin TSOP(ll) 86pin TSOP(ll) Grade Commercial Commercial Commercial Pb Free Free Free * EOREX reserves the right to change products or specification without notice. Jul. 2006 1/……
