器件名称:
M74HC109B1R
功能描述:
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
文件大小:
249.56KB 共11页
简 介:
M54HC109 M74HC109 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS109 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC109F1R M74HC109M1R M74HC109B1R M74HC109C1R DESCRIPTION The M54/74HC109 is a high speed CMOS DUAL JK FLIP-FLOP WITH PRESET AND CLEAR fabri2 cated in silicon gate C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. In accordance with the logic level on the J and K input is device changes state on positive going transitions of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection December 1992 1/11 M54/M74HC109 PIN DESCRIPTION PIN No 1, 15 2, 4, 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 SYMBOL 1CLR, 2CLR 1J, 2J, 1K, 2K 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION Asynchronous Reset Direct Inpu……
