器件名称:
M74HC112_01
功能描述:
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
文件大小:
409.81KB 共12页
简 介:
M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR s s s s s s s HIGH SPEED : fMAX = 79MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 112 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC112B1R M74HC112M1R T&R M74HC112RM13TR M74HC112TTR DESCRIPTION The M74HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M74HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth table. Input data is transferred to the input on the negative going edge of the clock pulse. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC112 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 13 2, 12 3, 11 4, 10 5, 9 6, 7 15, 14 8 16 SYMBOL 1CK, 2CK NAME AND FUNCTION Clock Input(HIGH to LOW edge triggered) Data Inputs: Flip-Flop 1 1K, 2K and 2 Data Inputs: Flip-F……
