器件名称:
M74HC73M1R
功能描述:
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
文件大小:
323.47KB 共11页
简 介:
M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR s s s s s s s HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 73 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC73B1R M74HC73M1R T&R M74HC73RM13TR M74HC73TTR DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Depending on the logic level applied to J and K inputs, this device changes state on the negative going transition of clock input pulse (CK). The clear function is accomplished independently of the clock condition when the clear input (CLR) is taken low. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC73 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 5 2, 6 12, 9 13, 8 14, 7, 3, 10 11 4 SYMBOL 1CK, 2CK NAME AND FUNCTION Clock Input Asynchronous Reset 1CLR, 2CLR Inputs 1Q, 2Q True Flip-Flop Outputs Complement Flip-Flop 1Q, 2Q Outputs 1J, 2J, 1K, Synchronous Inputs 2K Flip-Flop 1 and 2 GND Ground (0V) Vcc Positive Supply Voltage TRUTH TABLE INPUTS CLR L H H H H H X : Don’t Care OUTPUTS FUNCTION K X L H L H X CK X Q ……
