器件名称:
M74HC76-1
功能描述:
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
文件大小:
508.59KB 共11页
简 介:
M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR s s s s s s s HIGH SPEED : fMAX = 67MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 76 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC76B1R M74HC76M1R T&R M74HC76RM13TR M74HC76TTR DESCRIPTION The M74HC76 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Depending on with the logic level at J and K inputs, this device changes state on the negative going transition of clock pulse (CK). CLEAR (CLR) and PRESET (PR) are independent of the clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC76 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 6 2, 7 3, 8 4, 9 10, 14 11, 15 16, 12 13 5 SYMBOL 1CK, 2CK NAME AND FUNCTION Clock Input(HIGH to LOW edge triggered) 1PR, 2PR Set Inputs (Active LOW) Asynchronous Reset 1CLR, 2CLR Inputs (Active LOW) Data Inputs: Flip-Flop 1 1J, 2J and 2 Complement Flip-Flop 1Q, 2Q Outputs 1Q, 2Q True Flip-Flop Outputs Data Inputs: Flip-Flop 1 1K, 2K and 2 GND Ground (0V) Vcc Positive Su……
