器件名称: MC74HC11
功能描述: Dual J-K Flip-Flop with Set and Reset
文件大小: 211.16KB 共6页
简 介:MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual J-K Flip-Flop with Set and Reset
High–Performance Silicon–Gate CMOS
The MC74HC112 is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip–flop is negative–edge clocked and has active–low asynchronous Set and Reset inputs. The HC112 is identical in function to the HC76, but has a different pinout. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Similar in Function to the LS112 Except When Set and Reset are Low Simultaneously Chip Complexity: 100 FETs or 25 Equivalent Gates
16
MC74HC112
N SUFFIX PLASTIC PACKAGE CASE 648–08
1
16 1
D SUFFIX SOIC PACKAGE CASE 751B–05
16 1
DT SUFFIX TSSOP PACKAGE CASE 948F–01
ORDERING INFORMATION MC74HCXXXN MC74HCXXXD MC74HCXXXDT Plastic SOIC TSSOP
LOGIC DIAGRAM
PIN ASSIGNMENT
CLOCK 1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET 1 RESET 2 CLOCK 2 K2 J2 SET 2 Q2
SET 1 K1 CLOCK 1 J1 RESET 1
4 2 1 3 15 6 Q1 5 Q1
K1 J1 SET 1 Q1 Q1 Q2 GND
SET 2 K2 CLOCK 2 J2 RESET 2
10 12 13 11 14 PIN 16 = VCC PIN 8 = GND 7 Q2 9 Q2
FUNCTION TABLE
Inputs Set L H L H H H H H H H Reset Clock H L L H H H H H H H X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q Q H L……
