器件名称:
MC74HC73D
功能描述:
Dual J-K Flip-Flop with Reset
文件大小:
170.82KB 共5页
简 介:
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active–low asynchronous reset. The MC74HC73 is identical in function to the HC107, but has a different pinout. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 92 FETs or 23 Equivalent Gates 14 1 MC74HC73 N SUFFIX PLASTIC PACKAGE CASE 646–06 14 1 D SUFFIX SOIC PACKAGE CASE 751A–03 ORDERING INFORMATION MC74HCXXN MC74HCXXD Plastic SOIC PIN ASSIGNMENT CLOCK 1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 J1 Q1 Q1 GND K2 Q2 Q2 LOGIC DIAGRAM 14 1 3 2 7 5 10 6 PIN 4 = VCC PIN 11 = GND 8 Q2 13 Q1 RESET 1 K1 J1 CLOCK 1 K1 RESET 1 J2 CLOCK 2 K2 RESET 2 12 VCC Q1 CLOCK 2 RESET 2 J2 9 Q2 FUNCTION TABLE Inputs Reset L H H H H H H H Clock X J X L L H H X X X K X L H L H X X X Outputs Q Q L H No Change L H H L Toggle No Change No Change No Change L H 10/95 Motorola, Inc. 1995 1 REV 6 v v ……
