器件名称:
M12L16161A-7BG
功能描述:
512K x 16Bit x 2Banks Synchronous DRAM
文件大小:
697.27KB 共30页
简 介:
ESMT Revision History Revision 0.1 (Oct. 23 1998) -Original Revision 0.2 (Dec. 4 1998) -Add 200MHZ Revision 1.0 (Dec. 10 1999) -Delete Preliminary -Rename the filename Revision 1.1 (Jan. 26 2000) -Add –5.5 Spec. Revision 1.2 (Apr. 25 2000) -Correct error typing of C1 dimension Revision 1.3 (Nov. 27 2000) -P5 Number of valid output data CAS Latency 3 2ea -P17. P19. P21 Read Command shift right 1CLK -P15. P19. P20 Precharge Command shift left 1CLK Revision 1.4 (Feb. 22 2001) -P6 modify tOH –6(2ns) & -7(2ns) Revision 1.5 (Jun. 4 2001) -P3. P4 modify DC current Revision 1.6(Sep. 7 2001) -P5 modify AC parameters Revision 1.7 (Mar. 20 2002) -P28 C1(Nom)=0.15mm0.127mm -P28 delete symbol=ZD Revision 1.8 (Dec. 16 2003) -Modify stand off=0.051~0.203mm Revision 1.9 (Mar. 05 2004) -Correct typing error of timing (tRC; tRP;tRCD) -Add tRRD timing chart Revision 2.0 (May. 10 2005) Add “Pb-free” to ordering information Revision 2.1 (Jul. 07 2005) -Modify ICC1, ICC2N, ICC3N, ICC4, ICC5 spec -Delete –5.5, -6, -8, -10 AC spec Revision 2.2 (Oct. 06 2005) -Add 60V FBGA Revision 2.3 (Nov. 15 2005) -Modify VFBGA 60Ball Total high spec Revision 2.4 (May. 03 2007) - Delete BGA ball name of packing dimensions M12L16161A Elite Semiconductor Memory Technology Inc. Publication Date : May. 2005 Revision : 2.4 1/30 ESMT SDRAM M12L16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle wit……
