器件名称:
M12L32162A-7BG
功能描述:
1M x 16Bit x 2Banks Synchronous DRAM
文件大小:
702.79KB 共29页
简 介:
ESMT Revision History Revision 0.1 (Aug. 11 2006) - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Preliminary M12L32162A Revision 0.3 (Apr. 27 2007) - Rename BGA pin name (BA1 to NC; BA0 to BA) - Modify DC Characteristics Elite Semiconductor Memory Technology Inc. Publication Date : Apr. 2007 Revision : 0.3 1/29 ESMT SDRAM Preliminary M12L32162A 1M x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) GENERAL DESCRIPTION The M12L32162A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 1,048,576 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. z z z z z ORDERING INFORMATION Part NO. M12L32162A-7TG M12L32162A-7BG MAX Freq. 143MHz 143MHz PACKAGE COMMENTS 54PIN TSOP(II) 50 Ball BGA Pb-free Pb-free PIN……
