器件名称:
M12S16161A-10TG
功能描述:
512K x 16Bit x 2Banks Synchronous DRAM
文件大小:
871.76KB 共28页
简 介:
ESMT SDRAM M12S16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES 2.5V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (1, 2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation Special Function Support. PASR (Partial Array Self Refresh ) TCSR (Temperature compensated Self Refresh) DS (Driver Strength) DQM for masking Auto & self refresh 32ms refresh period (2K cycle) GENERAL DESCRIPTION The M12S16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. M12S16161A-10T M12S16161A-15T M12S16161A-10TG M12S16161A-15TG MAX Freq. 100MHz 66MHz 100MHz 66MHz Interface Package Comments Non-Pb-free 50 Non-Pb-free TSOP(II) Pb-free Pb-free LVCMOS PIN CONFIGURATION (TOP VIEW) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4……
