器件名称:
M52D16161A-10TG
功能描述:
512K x 16Bit x 2Banks Synchronous DRAM
文件大小:
756.5KB 共29页
简 介:
ESMT SDRAM M52D16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (1, 2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation Special Function Support. PASR (Partial Array Self Refresh ) TCSR (Temperature compensated Self Refresh) DS (Driver Strength) DQM for masking Auto & self refresh 32ms refresh period (2K cycle) GENERAL DESCRIPTION The M52D16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. z z z z ORDERING INFORMATION Part NO. MAX Freq. Package Comments Pb-free Pb-free z z z M52D16161A-10TG 100MHz 50 PIN TSOP(II) M52D16161A-10BG 100MHz 60 Ball VFBGA PIN CONFIGURATION (TOP VIEW) 1 A VSS 2 DQ15 3 4 5 6 DQ0 7 VDD VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9……
