器件名称: M52D32321A
功能描述: 512K x 32Bit x 2Banks Synchronous DRAM
文件大小: 690.89KB 共29页
简 介:ESMT
Revision History :
Revision 1.0 (Nov. 02, 2006) -Original Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision 1.2 (May. 03, 2007) - Modify DC Characteristics Revision 1.3 (May. 14,2007) - Modify tSS (1.5ns => 2.5ns) and tSH(1ns => 1.5ns)
M52D32321A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007 Revision : 1.3 1/29
ESMT
SDRAM 512K x 32Bit x 2Banks
M52D32321A
Synchronous DRAM
FEATURES
z z z z 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (1, 2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation Special Function Support. PASR (Partial Array Self Refresh ) TCSR (Temperature compensated Self Refresh) DS (Driver Strength) DQM for masking Auto & self refresh 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M52D32321A is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 32 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performa……
