器件名称:
M52S16161A
功能描述:
512K x 16Bit x 2Banks Synchronous DRAM
文件大小:
755.31KB 共29页
简 介:
ESMT SDRAM M52S16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z 2.5V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs CAS Latency (1, 2 & 3 ) Burst Length (1, 2, 4, 8 & full page) Burst Type (Sequential & Interleave) EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation Special Function Support. PASR (Partial Array Self Refresh ) TCSR (Temperature compensated Self Refresh) DS (Driver Strength) DQM for masking Auto & self refresh 32ms refresh period (2K cycle) GENERAL DESCRIPTION The M52S16161A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. z z z z ORDERING INFORMATION Part NO. M52S16161A-8TG M52S16161A-10TG M52S16161A-8BG M52S16161A-10BG MAX Freq. 125MHz 100MHz 125MHz 100MHz Interface Package Comments LVCMOS LVCMOS LVCMOS LVCMOS 50 TSOP(II) 50 TSOP(II) 60 Ball VFBGA 60 Ball VFBGA Pb-free Pb-free Pb-free Pb-free z z z PIN CONFIGURATION (TOP VIEW) 1 2 DQ15 3 4 5 6 DQ0 7 VDD VDD ……
