器件名称:
M74HC139C1R
功能描述:
M54HC138F1R M74HC138M1R M74HC138B1R M74HC138C1R
文件大小:
239.25KB 共9页
简 介:
M54HC139 M74HC139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER . . . . . . . . HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS139 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC139F1R M74HC139M1R M74HC139B1R M74HC139C1R DESCRIPTION The M54/74HC139 is a high speed CMOS DUAL TWO LINE TO FOUR LINE DECODER/DEMULTIPLEXER fabricated in silicon gate C 2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The active low enable input can be used for gating or as a data input for demultiplexing applications. While the enable input is held high, all four outputs are high independently of the other inputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection February 1993 1/9 M54/M74HC139 TRUTH TABLE INPUTS ENABLE SELECT G B A H X X L L L L L H L H L L H H OUTPUTS Y0 H L H H H Y1 H H L H H Y2 H H H L H Y3 H H H H L SELECTED OUTPUT NONE Y0 Y1 Y2 Y3 IEC LOGIC SYMBOL PIN DESCRIPTION PIN No 1, 15 2, 3 4, 5, 6, 7 12, 1……
