器件名称:
M74HC279RM13TR
功能描述:
QUAD S - R LATCH
文件大小:
283.12KB 共10页
简 介:
M74HC279 QUAD S - R LATCH s s s s s s s HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 279 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC279B1R M74HC279M1R T&R M74HC279RM13TR M74HC279TTR DESCRIPTION The M74HC279 is an high speed CMOS QUAD S - R LATCH fabricated with silicon gate C 2MOS technology. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/10 M74HC279 IINPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 5, 10, 14 2, 3, 6, 11, 12, 15 4, 7, 9, 13 8 16 SYMBOL 1R to 4R 1S1, 1S2, 2S, 3S1, 3S2, 4S 1Q to 4Q GND VCC NAME AND FUNCTION Reset Inputs (Active Low) Set Inputs (Active Low) Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE S# H L H L R H H L L Q Q0 H L H NOTE : Q0 = The level of Q before the indicated input condition was established. # : For latches with double S input : H : Both S inputs high L : One of both inputs low LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 M74HC279 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Di……
