器件名称:
M74HC4017B1R
功能描述:
DECADE COUNTER/DIVIDER
文件大小:
258.87KB 共12页
简 介:
M54HC4017 M74HC4017 DECADE COUNTER/DIVIDER . . . . . . . . HIGH SPEED tPD = 21 ns (typ.) AT VCC = 5V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 oC HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLEWITH 4017B B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC4017F1R M74HC4017M1R M74HC4017B1R M74HC4017C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC4017 is a high speed CMOS DECADE COUNTER/DIVIDER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M54/74HC4017 is a 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition of the clock input. Each output stays high for one clock period of the 10 clock period cycle. The CARRY output goes low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET input is also provided which when taken high sets all the decoded outputs low. NC = No Internal Connection Q3 October 1992 1/12 M54/M74HC4017 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE……
