器件名称:
M74HC4028M1R
功能描述:
BCD TO DECIMAL DECODER
文件大小:
245.14KB 共10页
简 介:
M54HC4028 M74HC4028 BCD TO DECIMAL DECODER . . . . . . . . HIGH SPEED tPD = 18 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 4028B B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC4028F1R M74HC4028M1R M74HC4028B1R M74HC4028C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC4028 is a high speed CMOS BCDTO-DECIMAL DECODER fabricated in silicon gate 2 C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. A BCD code applied to the four inputs (A to D) provides a high level at the selected one of the decimal decoded outputs. An illegal BCD code such as eleven to fifteen gives a low level at all outputs. The device also can be used as 3-TO8-LINE DECODER, when D input is assigned as a disable input. The device is useful for code conversion, address decoding, memory selection, demultiplexing, or read out decoding. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992 NC = No Internal Connection 1/10 M54/M74HC4028 TRUTH TABLE INPUTS D L L L L L L L L H H H H C L L L L H H H H L L X H B L L H H L L H H L ……
